1. Field of the Invention
The present invention relates to a production method of a semiconductor device and more particularly, to a production method of a semiconductor device having a wiring layer containing mainly gold (Au).
2. Description of the Related Art
A multilayer wiring film containing a gold layer has been largely expected to be suited to high density semiconductor devices due to the fact that it has superior characteristics such as low electric resistance, high resistance to migration and so on. With the wiring film, however, there arises such a large problem that cannot provide a good adhesion between the wiring film and a dielectric or insulation film formed thereon. Under such a circumstance, a lot of sorts of techniques have been developed in order to solve such the problem as follows;
(1) An adhesion dielectric film having a good adhesion property is formed on the multilayer wiring film and then, an insulator film is formed thereon thereby to enhance the adhesion between the wiring and insulator films. The adhesion dielectric layer is made of (A) an inorganic material or (B) an organic material. PA1 (2) An adhesion metal film having a good adhesion property is formed on the multilayer wiring film and then, an insulator film is formed thereon thereby to enhance the adhesion between the wiring and insulator films. The adhesion metal film is made by (A) a selective growth method or (B) a patterning metal film formed over the entirety of a semiconductor substrate.
FIGS. 1A and 1B cross-sectionally show a semiconductor device according to the above technique (1)(A), which is disclosed in "Solid State Technology", December 1983, pp. 137 to 141,
First, as shown in FIG. 1A, on a silicon substrate 401 a silicon dioxide film 402 is formed by a thermal oxidation or plasma-enhanced Chemical Vapor Deposition (CVD) technique. Subsequently, a film 403 made of an Titanium and tungsten (Ti--W) alloy having a 10% Ti content is formed thereon by a Direct Current (DC) magnetron sputtering technique, and a palladium (Pd) film 404 is formed thereon by the same DC magnetron sputtering technique.
Next, a photoresist film is selectively formed on the Pd film 404 by a photo-lithography technique. With the photoresist film as a mask, a gold (Au) film 406 is selectively formed on the Pd film 404 by an electrolytic plating technique. The photoresist film is removed, and then the Pd film 404 and the Ti--W film 403 are successively etched off with the plated Au film 406 as a mask. As a result, the multilayer wiring film composed of the Ti--W film 403, Pd film 404 and plated Au film 406 is obtained as shown in FIG. 1A.
Next, in order to improve the adhesion between the multilayer wiring film and an oxide film 411, on the top and side surfaces of the wiring film and the exposed surface of the silicon dioxide film 401, an adhesion layer 412 made of a plasma-deposited silicon nitride film, which is evaluated to be comparatively intimately adhesive to gold, is formed at a thickness of 25 to 30 nm.
Finally, the plasma-deposited silicon dioxide film 411 is formed on the adhesion layer 412 at a thickness of about 750 nm. Thus, the structure shown in FIG. 1B is obtained.
A gold film may be used instead of the Pd film 404.
In this case, the adhesion layer 412 of plasma-deposited silicon nitride is formed by the plasma-enhanced CVD technique under the conditions that source gas flows are at the ratio of SiH.sub.4 /NH.sub.3 /N.sub.2 =205/280/580 sccm, an atmosphere temperature is 300.degree. C., a gas pressure is 0.23 Torr and an input electric power is 500 W. The film 411 of plasma-deposited silicon oxide is formed by the plasma-enhanced CVD technique under the condition that gas flows are at the ratio of SiH.sub.4 /N.sub.2 O=70/1900 sccm, an atmosphere temperature is 300.degree. C., a gas pressure is 0.38 Torr and an input electric power is 500 W.
FIG. 2 cross-sectionally shows a semiconductor device according to the above technique (2)(A), which is disclosed by K. Mikagi et. al. in "Proceedings of 6th IEEE V-MIC conference", Jun. 1989, pp. 33 to 39.
This semiconductor device is similar to that in FIGS. 1A and 1B excepting the composition and forming process of an adhesion layer 512 and a second dielectric film 511 formed on the gold wiring. Components of the device in FIG. 2 having the same functions as those in FIGS. 1A and 1B are indicated by the same reference numerals and their explanations will be omitted for the sake of simplification.
First, a multilayer wiring film made of a Ti--W film 403, a Pd film 404 and an plated Au film 406 is formed on a silicon substrate 401 through the same processes as those in FIGS. 1A and 1B.
Next, an adhesion layer 512 of tungsten (W) is selectively formed on only the top surface of the multilayer wiring film by a CVD technique using tungsten fluoride (WF.sub.6) as a source gas and hydrogen silicide or silane (SiH.sub.4) as a reducing gas. A insulator film 511 of an organic material is formed on the entire surface of the W adhesion layer 512 and the exposed surface of a silicon dioxide film 402. Thus, the structure shown in FIG. 2 is obtained.
Due to the W adhesion layer 512 the adhesion between the multilayer wiring film and the organic insulator film 511 can be improved.
In the paper by K. Mikagi et. al., in the CVD process for forming selectively the tungsten film 512, a cold-wall type reaction chamber is employed, and the CVD process is preferably carried out under the conditions that an atmosphere temperature is 180.degree. to 250.degree. C., source gas flows are at the ratio of WF.sub.6 /(WF.sub.6 +SiH.sub.4)=0.4 to 0.6 and a gas pressure is 10 to 100 mTorr from the viewpoints of growth selectivity and quality of the tungsten film 512.
In addition, the following techniques can be employed for obtaining the adhesion layer; A first one is that the W adhesion layer of tungsten is formed by the reduction of tungsten fluoride (WF.sub.6) with hydrogen (H.sub.2) instead of the reduction of WF.sub.6 with hydrogen silicide (SiH.sub.4)
A second one is that a non-electrolytic plating technique is employed. In the non-electrolytic plating technique, for example, the Si substrate 401 containing the multilayer wiring film is immersed into a palladium chloride (PdCl.sub.2) solution as a pre-treatment and then, immersed into a non-electrolytic plating solution for obtaining the W adhesion layer 512. The plating solution is isothermally held and contains nickel sulfate as its main component and dimethylamine borane as a reducing agent and other additives, whose Ph is substantially neutral.
A third one is that a high adhesive conductor film is formed as an adhesion layer on the entire surface of the gold wiring, then patterned and thereafter, a dielectric film is formed thereon.
FIG. 3 is a cross-sectional view of a semiconductor device according to the above technique(2)(B), which is disclosed by K. Haberle, et. al. in "Proceedings of 5th IEEE V-MIC Conference", Jun. 1988, pp. 117 to 124.
First, a multilayer wiring film made of a Ti--W film 403, a Pd film 404 and an plated Au film 406 is formed on a silicon substrate 401 through the same processes as those in FIGS. 1A and 1B.
On the surface of the wiring film and the exposed surface of the silicon dioxide film 402 an adhesion layer 612 of chromium (Cr) is formed over the substrate 401. Then, the Cr adhesion layer is patterned to be left only on the top surface of the Au plated film 406. Subsequently, on the surface of the adhesion layer 612 and the exposed surface of the silicon dioxide film 402 a dielectric film 611 is formed. Thus, the structure shown in FIG. 3 is obtained.
The following technique is additionally described in the paper by K. Haberle as an adhesion layer made of an organic material is formed on the multilayer wiring film instead of that of an inorganic material shown in FIGS. 1A and 1B, which is corresponding to the above technique (1)(B).
The above-described conventional techniques individually have their own problems as follows;
In the case of the plasma-deposited silicon nitride film being employed as an adhesion layer, the film cannot always provide a sufficiently high adhesion property, so that the possibility of peeling between the wiring film and the adhesion layer due to thermal hysteresis during production process and/or deterioration with time in use exists. As a result, it is difficult to realize the multilayer wiring film at a high production yield, and a long-term reliability of the device cannot be obtained.
Furthermore, the adhesion layer made of plasma-deposited silicon nitride has a high dielectric constant and as a result, the interlayer capacity will be increased thereby to degrade the characteristics of the semiconductor device itself.
In the case where the adhesion layer is selectively grown by a CVD or non-electrolytic plating technique on the surface of the wiring film, a severe or strict process control is required and yet, even if the process is strictly controlled there is a possibility that the growth of the adhesion material such as tungsten does not become sufficiently selective. As a result, an interlayer short-circuit will occur and the production yield will be reduced.
In the case where the adhesion layer made of chromium or the like is selectively grown or formed on the multilayer wiring film, a large number of processes are required, and the production cost will be increased disadvantageously. In the case of patterning the adhesion layer of chromium or the like formed over the entirety of the substrate, it is difficult to apply this process to the minute wiring applications from the viewpoint of mask alignment accuracy and/or processing accuracy.
In the case of using an organic material as the adhesion layer, the insulator or dielectric film to be formed on the adhesion layer it is required for using an organic material for formation. However, any semiconductor device having the dielectric film of an organic material is not satisfactorily matched to the present semiconductor production process, and as a result, the degree of freedom of design will be lowered and there arises a disadvantageous problem on productivity.